Memory cell defects and memory array defects have many sources and, as a result, many signatures. While single, isolated cell failures may be spread throughout the array, very often, multiple cells in the same vicinity fail. When multi-cell failures occur, the failure may be characterized as a word line failure, (i.e. failing cells with the same word line address), a bit (or column) line failure (i.e. failing cells with the same bit address), or both. The sources of these multi-cell failures vary. Consequently, memory arrays are tested extensively to identify defective cells.
Very often, chips with defective cells can be repaired. Once identified, defective cells can be replaced, electrically, with spare cells, provided spare cells are included in the array. Providing on-chip spare cells to repair cell failures is known in the art as on-chip redundancy. A typical state of the art redundancy scheme has one or more spare rows (row redundancy) and/or one or more spare columns (column redundancy). These spare rows/columns have fuse programmable decoders that can be programmed to be responsive to the address of the defective row/column, while simultaneously disabling selection of the row/column with the defective cell. Electrically, a repaired chip cannot be discerned from a completely good chip.
FIG. 1 is a schematic representation of a prior art 16 Mb DRAM chip. The chip 100 is organized with two Redundant Bit Lines (RBL) 102 and 104 providing two spare columns in each subarray 106. Each subarray 106 includes 2.sup.n Bit Lines (BL) 108 (where n is typically between 5 and 8) and redundant bit lines (2 in this example). Each of the subarrays 106 is part of a subarray block 110. All of the subarray blocks 110, collectively, form the entire RAM array. So, for example, a 16 Mb RAM has 16 blocks 110 of 1 Mb each. Block size, subarray size and the number of subarrays 106 per block 110 are interdependent and, selected based on performance and logic objectives.
A subarray 106 is accessed when one word line 112 is selected and driven high. Data from accessed cells are provided simultaneously to the bit lines 108 and redundant bit lines 102 and 104. After a predetermined minimum delay, sufficient to allow the redundancy decoder to determine whether a spare column is addressed, a single bit line 108 or a redundant bit line 102, 104 is selected in each subarray 106. In each subarray, the selected bit line 108 or redundant bit line 102, 104 is coupled to a Local Data Line (LDL) 114. LDLs 114 are coupled to Master Data Lines (MDLs) 116. The MDLs 116 couple corresponding subarrays 106 in each subarray block 110. Data is transferred between the subarrays 106 and the chip I/O's on the MDLs 116.
FIG. 2A is a transistor level cross-sectional schematic of a subarray 106. Cells 120, 122 connected to adjacent word lines 112, 118 also are connected to opposite lines 124, 126 of each bit line pair. Thus, half of the word lines 112 (e.g., word lines with even addresses) select cells 120 on one line 124 of the bit line pair. While the remaining half of the word lines 118, (odd addressed word lines) select the cells 122 on the other lines 126 of the bit line pair. Each cell's storage capacitor 128 is, typically, a trench capacitor or a stacked structure for density. As is known in the art, the maximum voltage that an FET will pass is its gate to source voltage (V.sub.GS) reduced by the FET's turn-on or threshold voltage (V.sub.T), i.e., V.sub.GS -V.sub.T. So, if a bit line 124, 126 is charged to the supply voltage level V.sub.dd (or V.sub.H) and the word line 112, 118 is also at V.sub.dd, then the largest bit line signal, i.e., the voltage stored on or read from the storage capacitors 128, 138 is V.sub.dd -V.sub.T. Therefore, to maximize bit line signal, the word line 112, 118 is boosted during a read or a write, typically, to at least V.sub.dd +V.sub.T so that V.sub.dd is written into/read from the cell. This boosted level, called V.sub.pp, is normally generated on-chip.
Operation of the circuit of FIG. 2A is according to the timing diagram of FIG. 2B. A "one" is stored in the array such that it sets the sense amp in a predefined "one" condition. So, if a "one" is defined as 124 high and 126 low, then a "one" is stored in cell 120 (and all the other cells connected to 124) by charging the cell's storage capacitor 128. Conversely, a "one" is stored in 122 (and all other cells connected to 126) by charging that cell's storage capacitor 138. Prior to selecting a cell 120 or 122, the array is at its steady-state standby condition. The voltage on the bit line pair 124, 126 is equalized to V.sub.h /2, with the gate 132 of equalization transistor 134 held high. The Word Lines (WL) 112, 118 and Column Select (CSL) lines 146 are held low during standby. In prior art RAMs, each word line was clamped low (unless driven high) by a simple resetable latch (not shown). When a word line 112 (or 118) is driven high, cell pass gate 130 is turned on in each cell 120 on the word line 112, coupling the cell's storage capacitor 128 to line 124 of the pair. Thus charge is transferred between the storage capacitor 128 and line 124. Typically, bit line capacitance is at least one order of magnitude larger than that of the storage capacitor 128. So, the voltage on line 124 rises slightly if a one is stored on storage capacitor 128 or it falls slightly if a zero is stored on the storage capacitor 128. To maximize charge transfer between the bit line 124 and the storage capacitor 128, the word line 112 is boosted to V.sub.pp .gtoreq.V.sub.dd +V.sub.t. The other line 126 of the bit line pair remains at its pre-charge voltage level V.sub.dd /2 and, serves as a reference voltage for the Sense Amplifier 140.
After a delay sufficient that enough charge is transferred to sense "1" or "0", the sense amplifier 140 is set. The sense amp is set by driving both the Sense Amp Enable (SAE) line 142 high and its inverse 144 low. Data transferred to the bit line pair 124, 126 is amplified and redriven on the bit line pair, 124, 126 by setting the sense amplifier forcing 124, 126 High/Low or Low/High depending on data stored in the cell 120. Setting the sense amp, writes the sensed data back into the selected cell 120. Once all of the bit lines 124, 126 have been redriven by setting the Sense Amplifier, SEGment select signal (SEGEi) rises driving CSL 146 high to select a single column in each accessed subarray 106. A high on CSL 146 connects the selected redriven bit line pair 124, 126 to the LDLs 148, 150 through pass gates 152, 154. CSL timing is substantially identical to SEGE.sub.i but slightly delayed therefrom.
Testing a memory chip to identify failed cells is complicated, requiring special test patterns, designed for identifying each type of failure. Cell defects or weaknesses may cause either hard DC failures or AC (coupling) failures. Typical DC failures are: Leakage between a cell and a Passing Word Line(WL); Bit Line(BL) to WL leakage; WL to Substrate/channel leakage; or, WL to WL leakage. Typical AC failures are noise resulting from capacitive coupling to a WL or Sense Amp (SA) Set.
Many such tests require the simultaneous activation of several word lines in order to reduce test time and, therefore, to reduce cost. One example is the Multiple Word Line Select Test used to test for leakage between cell and a passing WL and between BL and WL. For this test, typically, one or more, but not all, word lines are driven high (activated), simultaneously, while setting the Sense Amps (SA). The activated word lines are held active for an extended period of time (long t.sub.RAS). For certain defects, cell leakage from a passing activated word line will charge the defective cell's storage capacitor 128, thereby changing the data stored in the cell. Also, for other types of defects, bit line to cell leakage will discharge the defective cell's charged storage capacitor 128, to reduce the stored charge, making the defective cell impossible, or nearly impossible to read and, therefore, identifiable. Since each word line needs to be activated for a relatively long time and because the DRAMs have a large number of word lines, many word lines must be activated simultaneously in this test in order to reduce test time.
Another example is the Transfer Gate Stress Test is used to identify cells with defective or weak gate oxide. For this test, typically, all of the word lines are driven high, above V.sub.H, e.g. to V.sub.pp, while all of the bit lines are forced low, to GND. With all of the word lines at V.sub.pp and all bit lines at GND, the gate oxide electric field is maximum. If a gate has defective or weak oxide, a short will form.
Often, tests involving multiple word lines are hampered by abnormally large plate voltage bounce on the storage capacitor plate or by array well voltage bounce, both of which result from simultaneously switching multiple word lines in these prior art DRAMs. These voltage bounces can cause abnormal disturbance to the cells under stress and destroy the data stored in the cell.
Another problem of simultaneously activating multiple word lines is the high probability of word line shorts which can reduce local V.sub.pp level through an IR drop. If for example, a word line is shorted to ground, the voltage drop across the supply bus resistance may be very significant. Also, word line to word line shorts may occur. Such shorts produce unreliable and unpredictable test results. However, in prior art DRAMs, selecting defective word lines, even if previously identified and replaced, is unavoidable during the above multiple word line tests. Thus, there is a need for RAMs wherein multiple word lines may be tested more easily, flexibly and reliably.